Cypress CY62158E Uživatelský manuál

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CY62158E MoBL
®
8-Mbit (1M x 8) Static RAM
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05684 Rev. *D Revised June 16, 2008
Features
Very high speed: 45 ns
Wide voltage range: 4.5V – 5.5V
Ultra low active power
Typical active current:1.8 mA @ f = 1 MHz
Typical active current: 18 mA @ f = f
max
Ultra low standby power
Typical standby current: 2 μA
Maximum standby current: 8 μA
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 44-Pin TSOP II package
Functional Description
The CY62158E MoBL
®
is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption significantly when deselected (CE
1
HIGH or
CE
2
LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. Data on the eight IO
pins (IO
0
through IO
7
) is then written into the location specified
on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and OE LOW while forcing the WE HIGH. Under these
conditions, the contents of the memory location specified by the
address pins appear on the IO pins.
The eight input and output pins (IO
0
through IO
7
) are placed in
a high impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE
1
LOW and CE
2
HIGH and WE
LOW). See the Truth Table on page 8 for a complete description
of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A
15
A
16
ROW DECODER
COLUMN DECODER
1024K x 8
ARRAY
DATA IN DRIVERS
A
10
A
11
A
17
CE
1
CE
2
A
12
A
18
A
19
Logic Block Diagram
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Shrnutí obsahu

Strany 1 - 8-Mbit (1M x 8) Static RAM

CY62158E MoBL®8-Mbit (1M x 8) Static RAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #: 38-

Strany 2

Document #: 38-05684 Rev. *D Revised June 16, 2008 Page 10 of 10All products and company names mentioned in this document may be the trademarks of the

Strany 3

CY62158E MoBL®Document #: 38-05684 Rev. *D Page 2 of 10Pin ConfigurationFigure 1. 44-Pin TSOP II (Top View) [1]Product Portfolio Product VCC Range (V

Strany 4

CY62158E MoBL®Document #: 38-05684 Rev. *D Page 3 of 10Maximum RatingsExceeding the maximum ratings may impair the useful life of thedevice. These use

Strany 5

CY62158E MoBL®Document #: 38-05684 Rev. *D Page 4 of 10Figure 2. AC Test Loads and WaveformsParameters 5.0V UnitR1 1838 ΩR2 994 ΩRTH645 ΩVTH1.75 VDat

Strany 6

CY62158E MoBL®Document #: 38-05684 Rev. *D Page 5 of 10Switching CharacteristicsOver the Operating Range[9]Parameter Description45 nsUnitMin MaxRead C

Strany 7

CY62158E MoBL®Document #: 38-05684 Rev. *D Page 6 of 10Switching WaveformsFigure 4 shows address transition controlled read cycle waveforms.[13, 14]Fi

Strany 8

CY62158E MoBL®Document #: 38-05684 Rev. *D Page 7 of 10Figure 6 shows WE controlled write cycle waveforms.[12, 16, 17]Figure 6. Write Cycle No. 1Figu

Strany 9

CY62158E MoBL®Document #: 38-05684 Rev. *D Page 8 of 10Figure 8 shows WE controlled, OE LOW write cycle waveforms.[17]Figure 8. Write Cycle No. 3Trut

Strany 10 - CY62158E MoBL

CY62158E MoBL®Document #: 38-05684 Rev. *D Page 9 of 10Package DiagramsFigure 9. 44-Pin TSOP II, 51-8508751-85087-*A[+] Feedback

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