Cypress CY7C1394BV18 Uživatelský manuál stáhnout pdf (Strana 1)

18-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

CY7C1392BV18, CY7C1992BV18

CY7C1393BV18, CY7C1394BV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05623 Rev. *D Revised June 2, 2008

Features

■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1392BV18 – 2M x 8

CY7C1992BV18 – 2M x 9

CY7C1393BV18 – 1M x 18

CY7C1394BV18 – 512K x 36

Functional Description

The CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and

CY7C1394BV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with Double Data Rate Separate IO (DDR-II SIO)

architecture. The DDR-II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR-II

SIO has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common IO devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K

. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K

if C/C are not provided. Each address

location is associated with two 8-bit words in the case of

CY7C1392BV18, two 9-bit words in the case of

CY7C1992BV18, two 18-bit words in the case of

CY7C1393BV18, and two 36-bit words in the case of

CY7C1394BV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ

, eliminating the need to capture

data separately from each individual DDR-II SIO SRAM in the

system design. Output data clocks (C/C

) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 820 770 700 575 485 mA

x9 825 775 700 575 490

x18 865 800 725 600 500

x36 935 850 770 630 540

[+] Feedback

1 2 3 4 5 6 ... 30 31

Shrnutí obsahu

Strany 1 - Burst Architecture

18-Mbit DDR-II SIO SRAM 2-WordBurst ArchitectureCY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Cypress Semiconductor Corporation • 198 Champion C

Strany 2

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 10 of 31Truth TableThe truth table for CY7C1392BV18, CY7C1992BV1

Strany 3

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 11 of 31Write Cycle DescriptionsThe write cycle description tabl

Strany 4

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 12 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incor

Strany 5

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 13 of 31IDCODEThe IDCODE instruction loads a vendor-specific, 32

Strany 6

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 14 of 31TAP Controller State DiagramThe state diagram for the TA

Strany 7

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 15 of 31TAP Controller Block DiagramTAP Electrical Characteristi

Strany 8

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 16 of 31TAP AC Switching Characteristics Over the Operating Rang

Strany 9

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 17 of 31Identification Register Definitions Instruction FieldVal

Strany 10 - CY7C1393BV18, CY7C1394BV18

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 18 of 31Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bu

Strany 11

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 19 of 31Power Up Sequence in DDR-II SRAMDDR-II SRAMs must be pow

Strany 12

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 2 of 31Logic Block Diagram (CY7C1392BV18)Logic Block Diagram (CY

Strany 13

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 20 of 31Maximum RatingsExceeding maximum ratings may impair the

Strany 14

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 21 of 31IDD [19]VDD Operating Supply VDD = Max,IOUT = 0 mA,f = f

Strany 15

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 22 of 31CapacitanceTested initially and after any design or proc

Strany 16 - [+] Feedback

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 23 of 31Switching Characteristics Over the Operating Range [20,

Strany 17

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 24 of 31Output TimestCOtCHQVC/C Clock Rise (or K/K in single clo

Strany 18

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 25 of 31Switching WaveformsFigure 5. Read/Write/Deselect Sequen

Strany 19 - DLL Constraints

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 26 of 31Ordering Information Not all of the speed, package, and

Strany 20 - Operating Range

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 27 of 31250 CY7C1392BV18-250BZC 51-85180 165-Ball Fine Pitch Bal

Strany 21

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 28 of 31167 CY7C1392BV18-167BZC 51-85180 165-Ball Fine Pitch Bal

Strany 22 - Thermal Resistance

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 29 of 31Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x 1.4 mm

Strany 23

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 3 of 31Logic Block Diagram (CY7C1393BV18)Logic Block Diagram (CY

Strany 24

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 30 of 31Document History PageDocument Title: CY7C1392BV18/CY7C19

Strany 25 - Switching Waveforms

Document #: 38-05623 Rev. *D Revised June 2, 2008 Page 31 of 31QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress

Strany 26

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 4 of 31Pin Configuration The pin configuration for CY7C1392BV18,

Strany 27

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 5 of 31CY7C1393BV18 (1M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ NC/144M

Strany 28

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 6 of 31Pin Definitions Pin Name IO Pin DescriptionD[x:0]Input-Sy

Strany 29

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 7 of 31CQ Echo Clock CQ is Referenced with Respect to C. This is

Strany 30

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 8 of 31Functional OverviewThe CY7C1392BV18, CY7C1992BV18, CY7C13

Strany 31

CY7C1392BV18, CY7C1992BV18CY7C1393BV18, CY7C1394BV18Document #: 38-05623 Rev. *D Page 9 of 31DLLThese chips use a Delay Lock Loop (DLL) that is design

Příbuzné modely CY7C1393BV18 | CY7C1392BV18 |

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Cypress CY7C1394BV18 Uživatelský manuál Strana 1

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Příbuzné modely CY7C1393BV18 | CY7C1392BV18 |

Komentáře k této Příručce

Cypress CY7C1394BV18 Uživatelský manuál Strana 1

Procházejte online nebo si stáhněte Uživatelský manuál pro Hardware Cypress CY7C1394BV18. Cypress CY7C1394BV18 User Manual Uživatelská příručka

Shrnutí obsahu

Příbuzné modely CY7C1393BV18 | CY7C1392BV18 |

Komentáře k této Příručce

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