Cypress CY7C145 Uživatelský manuál stáhnout pdf

CY7C145, CY7C144

8K x 8/9 Dual-Port Static RAM

with SEM, INT, BUSY

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-06034 Rev. *D Revised December 10, 2008

Features

■ True Dual-Ported memory cells that enable simultaneous

reads of the same memory location

■ 8K x 8 organization (CY7C144)

■ 8K x 9 organization (CY7C145)

■ 0.65-micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: I

= 160 mA (max.)

■ Fully asynchronous operation

■ Automatic power down

■ TTL compatible

■ Master/Slave select pin enables bus width expansion to

16/18 bits or more

■ Busy arbitration scheme provided

■ Semaphores included to permit software handshaking

between ports

■ INT flag for port-to-port communication

■ Available in 68-pin PLCC, 64-pin and 80-pin TQFP

■ Pb-free packages available

Functional Description

The CY7C144 and CY7C145 are high speed CMOS 8K x 8

and 8K x 9 dual-port static RAMs. Various arbitration schemes

are included on the CY7C144/5 to handle situations when

multiple processors access the same piece of data. Two ports

are provided permitting independent, asynchronous access

for reads and writes to any location in memory. The

CY7C144/5 can be used as a standalone 64/72-Kbit dual-port

static RAM or multiple devices can be combined in order to

function as a 16/18-bit or wider master/slave dual-port static

RAM. An M/S

pin is provided for implementing 16/18-bit or

wider memory applications without the need for separate

master and slave devices or additional discrete logic. Appli-

cation areas include interprocessor/multiprocessor designs,

communications status buffering, and dual-port

video/graphics memory.

Each port has independent control pins: chip enable (CE

read or write enable (R/W

), and output enable (OE). Two flags,

BUSY

and INT, are provided on each port. BUSY signals that

the port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT

) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from

one port to the other to indicate that a shared resource is in

use. The semaphore logic is comprised of eight shared

latches. Only one side can control the latch (semaphore) at

any time. Control of a semaphore indicates that a shared

resource is in use. An automatic power down feature is

controlled independently on each port by a chip enable (CE

)

pin or SEM

pin.

Notes

1. BUSY

is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

R/W

12L

12R

R/W

I/O7L

I/O

I/ O 7R

I/ O

INT ERRUPT

SEMAPHORE

AR B I TR AT IO N

CONTROL

I/ O

CONTROL

I/O

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

SE M

BUSY

L BU S Y

INT

M/S

(7C145) I/O

I/ O

(7 C 1 4 5

)

[1 , 2 ]

[2]

[1, 2]

[2]

Logic Block Diagram

CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM

with SEM, INT, BUSY

[+] Feedback

1 2 3 4 5 6 ... 20 21

CY7C145, CY7C144 10

Shrnutí obsahu

Strany 1

CY7C145, CY7C1448K x 8/9 Dual-Port Static RAMwith SEM, INT, BUSYCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 40

Strany 2

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 10 of 21Figure 10. Semaphore Read After Write Timing, Either Side[25]Figure 11. Semaphore Conten

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CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 11 of 21Figure 12. Read with BUSY (M/S=HIGH)[20]Figure 13. Write Timing with Busy Input (M/S=LOW

Strany 4

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 12 of 21Figure 14. Busy Timing Diagram No. 1 (CE Arbitration)[29]Figure 15. Busy Timing Diagram

Strany 5

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 13 of 21Figure 16. Interrupt Timing DiagramsNotes30. tHA depends on which enable pin (CEL or R/WL

Strany 6

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 14 of 21ArchitectureThe CY7C144/5 consists of a an array of 8K words of 8/9 bitseach of dual-port

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CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 15 of 21Table 3. Non-Contending Read/WriteInputs OutputsCE R/W OE SEM I/O0−7/8OperationH X X H Hi

Strany 8

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 16 of 21Figure 17. Typical DC and AC Characteristics1.41.00.44.0 4.5 5.0 5.5 6.0−55 25 1251.21.01

Strany 9

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 17 of 21Ordering Information8K x8 Dual-Port SRAMSpeed(ns) Ordering CodePackageName Package TypeOpe

Strany 10 - CY7C145, CY7C144

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 18 of 218K x9 Dual-Port SRAMSpeed(ns) Ordering CodePackageName Package TypeOperatingRange15 CY7C14

Strany 11

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 19 of 21Package DiagramsFigure 18. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 (51-

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CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 2 of 21Pin Configurations Figure 1. 68-Pin PLCC (Top View)Figure 2. 64-Pin PLCC (Top View)101112

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CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 20 of 21Figure 19. 80-Pin Thin Plastic Quad Flat Pack A80 (51-85065)Figure 20. 68-Pin Plastic Le

Strany 14

Document #: 38-06034 Rev. *D Revised December 10, 2008 Page 21 of 21All products and company names mentioned in this document may be the trademarks o

Strany 15

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 3 of 21Figure 3. 80-Pin TQFPPin Configurations (continued)12345678910111213141517161819202122232

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CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 4 of 21Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These use

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CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 5 of 21Electrical Characteristics Over the Operating Range (continued)Parameter Description Test C

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CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 6 of 21Figure 4. AC Test Loads and Waveforms3.0VGND90%90%10%≤ 3ns≤ 3 ns10%ALL INPUT PULSES(a) Nor

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CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 7 of 21tSDData Set-Up to Write End 10 15 15 25 nstHDData Hold From Write End 0 0 0 0 nstHZWE[11,12

Strany 20

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 8 of 21Switching Waveforms Figure 5. Read Cycle No. 1 (Either Port Address Access)[15, 16]Figure

Strany 21

CY7C145, CY7C144Document #: 38-06034 Rev. *D Page 9 of 21Figure 8. Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23]Figure 9.

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