Cypress CY62128EV30 Uživatelský manuál stáhnout pdf

CY62128EV30

MoBL® 1 Mbit (128K x 8) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05579 Rev. *D Revised March 28, 2008

Features

■ Very high speed: 45 ns

❐ Temperature ranges:

• Industrial: –40°C to +85°C

• Automotive-A: –40°C to +85°C

• Automotive-E: –40°C to +125°C

■ Wide voltage range: 2.20V – 3.60V

■ Pin compatible with CY62128DV30

■ Ultra low standby power

❐ Typical standby current: 1 μA

❐ Maximum standby current: 4 μA

■ Ultra low active power

❐ Typical active current: 1.3 mA @ f = 1 MHz

■ Easy memory expansion with CE

, CE

and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

■ Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin

STSOP packages

Functional Description

The CY62128EV30

[1]

is a high performance CMOS static RAM

module organized as 128K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL

) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device into standby mode reduces power consumption by more

than 99% when deselected (CE

HIGH or CE

LOW). The eight

input and output pins (IO

through IO

) are placed in a high

impedance state when the device is deselected (CE

HIGH or

LOW), the outputs are disabled (OE HIGH), or a write

operation is in progress (CE

LOW and CE

HIGH and WE

LOW).

To write to the device, take Chip Enable (CE

LOW and CE

HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO

pins is then written into the location specified on the Address pin

through A

To read from the device, take Chip Enable (CE

LOW and CE

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE

) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the IO pins.

SENSE AMPS

POWER

DOWN

ROW DECODER

COLUMN DECODER

128K x 8

ARRAY

INPUT BUFFER

Logic Block Diagram

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

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Shrnutí obsahu

Strany 1 - CY62128EV30

CY62128EV30MoBL® 1 Mbit (128K x 8) Static RAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #

Strany 2

CY62128EV30Document #: 38-05579 Rev. *D Page 10 of 11Figure 9. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094Package Diagrams (cont

Strany 3

Document #: 38-05579 Rev. *D Revised March 28, 2008 Page 11 of 11MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semi

Strany 4 - THEVENIN EQUIVALENT

CY62128EV30Document #: 38-05579 Rev. *D Page 2 of 11 Pin Configuration[2]A6A7A16A14A12WEVCCA4A13A8A9OESTSOPTop View(not to scale)30282931241923222120

Strany 5

CY62128EV30Document #: 38-05579 Rev. *D Page 3 of 11Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These user guide

Strany 6

CY62128EV30Document #: 38-05579 Rev. *D Page 4 of 11Capacitance (For all packages)[8]Parameter Description Test Conditions Max UnitCINInput Capacitanc

Strany 7

CY62128EV30Document #: 38-05579 Rev. *D Page 5 of 11 Data Retention Waveform [10]Switching Characteristics (Over the Operating Range)[10, 11]Paramete

Strany 8

CY62128EV30Document #: 38-05579 Rev. *D Page 6 of 11Switching WaveformsFigure 2. Read Cycle 1 (Address transition controlled) [15, 16]Figure 3. Read

Strany 9 - 51-85056-*D

CY62128EV30Document #: 38-05579 Rev. *D Page 7 of 11 Figure 5. Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19]Figure 6. Write Cycle No. 3

Strany 10 - 51-85094-*D

CY62128EV30Document #: 38-05579 Rev. *D Page 8 of 11 Ordering InformationSpeed(ns)Ordering CodePackageDiagramPackage TypeOperatingRange45 CY62128EV30L

Strany 11

CY62128EV30Document #: 38-05579 Rev. *D Page 9 of 11Figure 8. 32-Pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056Package Diagrams (continu