Cypress CY7C1312BV18 Uživatelský manuál stáhnout pdf (Strana 3)

CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Document #: 38-05619 Rev. *F Page 3 of 29

Logic Block Diagram (CY7C1312BV18)

Logic Block Diagram (CY7C1314BV18)

512K x 18 Array

CLK

A

(18:0)

Gen.

K

K

Control

Logic

Address

Register

D

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Register

Reg.

Reg.

Reg.

18

19

36

18

BWS

[1:0]

V

REF

Write Add. Decode

Write

Reg

18

A

(18:0)

19

CQ

CQ

DOFF

Q

[17:0]

18

18

18

Write

Reg

C

C

512K x 18 Array

256K x 36 Array

CLK

A

(17:0)

Gen.

K

K

Control

Logic

Address

Register

D

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Register

Reg.

Reg.

Reg.

36

18

72

36

BWS

[3:0]

V

REF

Write Add. Decode

Write

Reg

36

A

(17:0)

18

CQ

CQ

DOFF

Q

[35:0]

36

36

36

Write

Reg

C

C

256K x 36 Array

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