Cypress CY7C1318JV18 Uživatelský manuál stáhnout pdf (Strana 1)

18-Mbit DDR-II SRAM 2-Word

Burst Architecture

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-15271 Rev. *B Revised March 10, 2008

Features

■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1316JV18 – 2M x 8

CY7C1916JV18 – 2M x 9

CY7C1318JV18 – 1M x 18

CY7C1320JV18 – 512K x 36

Functional Description

The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and

CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a one-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K

. Read data is

driven on the rising edges of C and C

if provided, or on the rising

edge of K and K

if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1316JV18

and two 9-bit words in the case of CY7C1916JV18 that burst

sequentially into or out of the device. The burst counter always

starts with a ‘0’ internally in the case of CY7C1316JV18 and

CY7C1916JV18. For CY7C1318JV18 and CY7C1320JV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words (in the case of

CY7C1318JV18) of two 36-bit words (in the case of

CY7C1320JV18) sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz Unit

Maximum Operating Frequency 300 MHz

Maximum Operating Current x8 610 mA

x9 615

x18 655

x36 730

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 25 26

Shrnutí obsahu

Strany 1 - Burst Architecture

18-Mbit DDR-II SRAM 2-WordBurst ArchitectureCY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Cypress Semiconductor Corporation • 198 Champion Court

Strany 2

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 10 of 26Truth TableThe truth table for the CY7C1316JV18, C

Strany 3

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 11 of 26Write Cycle DescriptionsThe write cycle descriptio

Strany 4

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 12 of 26IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs

Strany 5

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 13 of 26IDCODEThe IDCODE instruction loads a vendor-specif

Strany 6

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 14 of 26TAP Controller State DiagramThe state diagram for

Strany 7

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 15 of 26TAP Controller Block DiagramTAP Electrical Charact

Strany 8

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 16 of 26TAP AC Switching Characteristics Over the Operatin

Strany 9

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 17 of 26Identification Register Definitions Instruction Fi

Strany 10 - CY7C1318JV18, CY7C1320JV18

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 18 of 26Boundary Scan Order Bit # Bump ID Bit # Bump ID Bi

Strany 11

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 19 of 26Power Up Sequence in DDR-II SRAMDDR-II SRAMs must

Strany 12

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 2 of 26Logic Block Diagram (CY7C1316JV18)Logic Block Diagr

Strany 13

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 20 of 26Maximum RatingsExceeding maximum ratings may short

Strany 14

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 21 of 26CapacitanceTested initially and after any design o

Strany 15

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 22 of 26Switching Characteristics Over the Operating Range

Strany 16 - [+] Feedback [+] Feedback

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 23 of 26Switching WaveformsFigure 3. Read/Write/Deselect

Strany 17

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 24 of 26Ordering Information Not all of the speed, package

Strany 18

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 25 of 26Package DiagramFigure 4. 165-ball FBGA (13 x 15 x

Strany 19 - Power Up Waveforms

Document Number: 001-15271 Rev. *B Revised March 10, 2008 Page 26 of 26QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Strany 20

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 3 of 26Logic Block Diagram (CY7C1318JV18)Logic Block Diagr

Strany 21 - AC Test Loads and Waveforms

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 4 of 26Pin ConfigurationThe pin configuration for CY7C1316

Strany 22

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 5 of 26CY7C1318JV18 (1M x 18)1234567891011A CQNC/72M A R/W

Strany 23

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 6 of 26Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]I

Strany 24

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 7 of 26CQ Output Clock CQ is Referenced with Respect to C.

Strany 25 - Package Diagram

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 8 of 26Functional OverviewThe CY7C1316JV18, CY7C1916JV18,

Strany 26 - Document History Page

CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18Document Number: 001-15271 Rev. *B Page 9 of 26driver impedance. The value of RQ must be 5x the va

Příbuzné modely CY7C1320JV18

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Cypress CY7C1318JV18 Uživatelský manuál Strana 1

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