Cypress DCT-1D Uživatelská příručka stáhnout pdf (Strana 30)

CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUS

4. simulate the computer running the benchmark program.

5. design a module containing hardware performance counters (perf_top.sv in

the lab skeleton).

3.2 Some Basic Facts on the Wishbone Bus

The Wishbone bus is intended for implementation in FPGAs or ASICs. Typical for

such a bus is that multiplexers are used instead of tristate buffers. Two data buses are

used, one for each direction, see Figure 3.2a.

Master Slave

wb.stb

wb.cyc

wb.ack

wb.dat_o

wb.dat_i

wb.adr

(a) A Wishbone Master/Slave inter-

face.

wb.dat_o

wb.stb

wb.cyc

wb.we

wb.ack

clk

wb.adr

(b) A Wishbone write cycle.

wb.we

wb.stb

wb.cyc

wb.ack

wb.dat_i

wb.adr

Figure 3.2: The Wishbone bus protocol.

In this lab we will only need a subset of the Wishbone protocol, namely the basic

write and read bus cycles.

For the write cycle, see Figure 3.2b, we have:

1. The master places address and data on the buses wb.adr and wb.dat_o, re-

spectively. Finally the master asserts the wb.stb-signal, wb.cyc-signal, and

wb.we-signal.

2. The slave, when ready, decodes the address bus, latches the data and asserts the

wb.ack-signal.

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Cypress DCT-1D Uživatelská příručka Strana 30