Cypress DCT-1D Uživatelská příručka stáhnout pdf (Strana 45)

4.2. PROPOSED ARCHITECTURE

to use a block RAM is, in our opinion, to instantiate a library primitive. The code in

Listing 4.1 instantiates a block RAM shown in Figure 4.2.

SSR is a set/reset signal, that only affects the output latches, not the RAM mem-

ory cells. DIP and DOP can be used for additional data such as parity bits but we do

not use them in this lab. It is important to understand that both reads and writes are

synchronous as opposed to an ordinary RAM that you might have used in one of our

earlier courses such as Digital Konstruktion.

Listing 4.1: Instantiation of a block RAM as shown in Figure 4.2

wi r e [ 3 1 : 0 ] doa , d i a , dob , di b ;

wi r e [ 8 : 0 ] a d dra , ad dr b ;

wi r e cl k , cea , wea , ceb , web ;

/ / d u a l p o r t 512 x32 RAM

RAM B16_S36_S36 mem ory (

/ / p o r t A

.DOA( doa ) , . DOPA ( ) , .ADDRA( a d d r a ) , . CLKA( c l k ) ,

. D IA ( d i a ) , . DIPA ( 4 ’ h0 ) , .ENA( ce a ) , . SSRA ( 1 ’ b0 ) , .WEA( wea ) ,

/ / p o r t B

.DOB( dob ) , . DOPB( ) , .ADDRB( a d d r b ) , . CLKB( c l k ) , . DIB ( d i b ) ,

. DIPB ( 4 ’ h0 ) , . ENB( ceb ) , . SSRB( 1 ’ b0 ) , .WEB( web ) ) ;

DIA DIB

DOA DOB

32 32

9 9

ADDRA

CLKA,ENA,

WEA

ADDRB

CLKB,ENB,

WEB

Figure 4.2: Dualported 512 × 32 bit block RAM.

4.2.2 Distributed RAMs

Small RAMs can be designed using the LUTs in the FPGA. A LUT is a 16 ×1 RAM.

Distributed RAM memory supports the following:

• Single-port RAM with one synchronous write and one combinatorial read port

• Dual-port RAM with one s ynchronous write port and two asynchronous read

ports

For instance a 16 × 8 RAM can be designed in Verilog as shown in Listing 4.2.

Listing 4.2: Distributed RAM instantiaton in Verilog.

re g [ 7 : 0 ] mem [ 1 5 : 0 ] ;

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 81 82

Žádné komentáře

Cypress DCT-1D Uživatelská příručka Strana 45