Cypress DCT-1D Uživatelská příručka stáhnout pdf (Strana 46)

CHAPTER 4. LAB TASK 2 - DESIGN A JPEG ACCELERATOR

wi r e [ 7 : 0 ] d a t a _ i , d a t a _ o ;

wi r e [ 3 : 0 ] a d d r_a , a d d r _ b ;

/ / 1 c o m b i n a t o r i a l r e a d p o r t

a s s i g n d a t a _ o = mem[ a d d r _ a ] ;

/ / 1 s y n c h r o n o u s w r i t e p o r t

al ways @( pose d ge c l k ) be g i n

i f ( we )

mem[ ad d r _ b ] <= d a t a _ i ;

end

4.2.3 The transpose memory

The transpose memory shall:

• be designed as a Verilog module, with the interface shown in Listing 4.3.

• hold an 8 × 8 × 12 bit image.

• allow writes of rows and reads of columns in one clock cycle.

• have no address inputs.

Listing 4.3: Transpose memory interface

module t r a n s p o s e ( i n p u t c l k , r s t , wr , rd ,

i n pu t [ 9 5 : 0 ] in , o u t p ut [ 9 5 : 0 ] u t ) ;

We leave it to the designer to decide how the signals wr, rd exactly work.

4.2.4 WB memory map

The accelerator shall have the memory map shown in Table 4.1. csr is the Control/Status

the accelerator is ready bit 7, the RDY bit, is set. The START bit is cleared by the DCT2

Control Unit and the RDY bit by software.

mem Base Address Size Read/Write

in 0x9600_0000 512 × 32 WO 32 bit

out 0x9600_0800 512 × 32 RO

csr 0x9600_1000 1 × 8 RW 8 bits

dma 0x9600_1800 For use in lab 3

Table 4.1: Accelerator memory map

Preparation task 7

Draw a block diagram of the transpose memory. Rows can be written and columns can

be read in 1 clock cycle.

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 81 82

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Cypress DCT-1D Uživatelská příručka Strana 46