Cypress DCT-1D Uživatelská příručka stáhnout pdf (Strana 57)

5.1. DMA IN THE DCT ACCELERATOR

• dma_bram_data:

The data we want to write to inmem in jpeg_top.

• dma_bram_addr:

The address we want to write the data to.

• dma_bram_we:

The write enable signal for inmem.

• dma_start_dct:

When this clock signal is high for one clock cycle, the DMA accelerator will

start to transform the current block in inmem.

• dct_busy:

This input signal is high from one clock cycle after dma_start_dct has been

activated to the moment all results have been written to outmem. (You have to

make sure that your DCT accelerator busy signal actually works like this.)

The interface to the address generator is as f ollows:

• resetaddr_i:

The address generator sets the address to the start address speciﬁed in dma_srcaddr.

• incaddr_i:

The address generator will increase the address to the next word we need to read.

• address_o:

The current address of the image.

• endframe_o:

This signal is active when the current address is the last address of the image.

• endblock_o:

This signal is active when the current address is the last address of an 8x8 block.

• endline_o:

This signal is active when the current address is the last address of a line of an

8x8 block.

• dma_srcaddr, dma_pitch, dma_endblock_x,dma_endblock_y:

As described above.

There are also some other important signals that are available such as:

• startfsm:

This signal is active when the CPU has written a 1 to bit 0 of the CONTROL

• startnextblock:

This signal is one when the CPU writes a 1 to bit 1 of the CONTROL register.

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Cypress DCT-1D Uživatelská příručka Strana 57